Ferroelectric memory devices and methods of using ferroelectric capacitors

ABSTRACT

A ferroelectric memory device has a ferroelectric memory capacitor with a hysteresis characteristic adapted to store either a first memory content corresponding to a first polarization condition or a second memory content corresponding to a second polarization condition when there is no applied voltage. A first load capacitor is connected in series with the memory capacitor, and a second load capacitor is connected in series with a reference capacitor. The first and second capacitors are both ferroelectric capacitors and have substantially the same characteristics as the memory capacitor. The ratio of area between the reference and second capacitors is such that Veff (the partial voltage which appears across the reference capacitor if a specified voltage is applied to the series connection of the reference capacitor and the second load capacitor) is nearly equal to the average of V1 (the partial voltage which appears across the memory capacitor if the specified voltage is applied to the series connection of the memory capacitor and the first load capacitor when the memory capacitor is in the first polarization condition) and V2 (the partial voltage which appears across the memory capacitor if the specified voltage is applied to the series connection of the memory capacitor and the first load capacitor when the memory capacitor is in the second polarization condition) or slightly closer to V1 from the average.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of my commonly assigned application Ser.No. 08/749,657 filed on Nov. 15, 1996, now U.S. Pat. No. 5,764,561.

BACKGROUND OF THE INVENTION

This invention relates to ferroelectric memory devices and, moreparticularly, to improvements in reliability of their readoutoperations. This invention also relates to methods of usingferroelectric capacitors and improving the useful endurance offerroelectric memory devices.

Ferroelectric memory devices using ferroelectric capacitors have beenknown as an example of non-volatile semiconductor memories. As shown inpart in FIG. 19, a prior art ferroelectric memory device includes aferroelectric capacitor 4 and a load capacitor 6, and the hysteresiscurve of the ferroelectric capacitor 4, representing the relationshipbetween the voltage (or the relative voltage of the bit line BL withrespect to the plate line PL at a reference potential) and thepolarization condition (represented by the "charge" which is itsequivalent) is shown in FIG. 20. With reference now to FIG. 20, letfirst and second polarization conditions denoted by P1 and P2respectively be the polarization condition of the ferroelectriccapacitor 4 when its remanent polarization is Z1 and Z2, correspondingto memory content "H" and "L" such that the memory content of theferroelectric capacitor 4 can be read by detecting whether theferroelectric capacitor 4 is in polarization condition Z1 or Z2.

For determining whether the ferroelectric capacitor 4 is in the first orsecond polarization condition, the load capacitor 6 shown in FIG. 19 isdischarged first and, after the bit line BL is in a floating condition,a readout voltage is applied to the plate line PL, and the voltagedifference Vf generated between the ends of the ferroelectric capacitor4 is measured. Let the slope of straight lines L1 in FIG. 20 representthe electrostatic capacitance of the load capacitor 6. If theferroelectric capacitor 4 was in the first polarization condition P1,the voltage difference Vf between the ends of the ferroelectriccapacitor 4 becomes V1, and if the ferroelectric capacitor 4 was in thesecond polarization condition P2, the voltage difference Vf will be V2.Thus, if the reference voltage Vref is set as shown in FIG. 20, it ispossible to determine whether the ferroelectric capacitor 4 was in thefirst or second polarization condition by comparing the voltage Vfbetween its ends at the time of a readout and the reference voltageVref.

In this situation, if the ferroelectric capacitor 4 is in the secondpolarization condition P2, there is no change in the remanentpolarization although its polarization condition temporarily becomes P3at the time of readout because the polarization condition returns to thesecond polarization condition P2 as the applied voltage returns to zero.If the ferroelectric capacitor 4 is in the first polarization conditionP1, however, its polarization condition temporarily becomes P4 at thetime of readout and then P5 as the applied voltage becomes zero, causinga change in the remanent polarization due to the readout. In view ofthis, a rewrite voltage Vrw is applied after the readout to theferroelectric capacitor 4, giving rise to the polarization condition P6such that, when the applied voltage returns to zero, the ferroelectriccapacitor 4 will return to the first polarization condition. In summary,a rewrite is carried out after the readout if the ferroelectriccapacitor 4 is in the first polarization condition P1 such that theremanent polarization is changed again and the ferroelectric capacitor 4is forcibly returned to the first polarization condition P1. This hasbeen the prior art method of preventing the change in the memory contentdue to the readout.

The useful endurance of a ferroelectric capacitor, however, isdetermined in part by the number of inversions in the spontaneouspolarization (or changes in the remanent polarization) and may be about10¹² times, although this depends on the ferroelectric material.Consider now a situation of reading out the same memory cell with memorycontent "H" (corresponding to the first polarization condition P1). Ifthe readout cycle is long such that the next readout is carried out onlyafter the ferroelectric capacitor 4 returns to the first polarizationcondition P1 after a rewrite by natural discharge, there is no problembecause the useful endurance can remain reasonably long. If the readoutcycle is short such that the next readout starts before naturaldischarge of the ferroelectric capacitor 4 can hardly take place after arewrite, it can be a problem from the point of view of useful enduranceof the ferroelectric capacitor 4.

With reference again to FIG. 20, the voltages V1 and V2 must be setsufficiently far away from the reference voltage Vref in order toprevent errors in the readout. For this reason, the electrostaticcapacitance of the load capacitor 6 (the slope of the lines L1) must berelatively large. Thus, the remanent polarization changes from P1 to P8to P1 even when the next readout is started before there is hardly anynatural discharge of the ferroelectric capacitor 4 (in polarizationcondition P6) after a rewrite. As a consequence, the number of times ofreadout from a same memory cell with memory content "H" comes to affectthe useful endurance. This is one of the problems of prior artferroelectric memory devices.

Moreover, the voltages V1 and V2 for a prior art ferroelectric memorydevice depend heavily on the hysteresis characteristic of itsferroelectric capacitor 4 and the electrostatic capacitance of the loadcapacitor 6, but there are large fluctuations in their values due, forexample, to variations in the conditions at their production. Thus, thevariations in voltages V1 and V2 are also large and, since the referencevoltage Vref, the readout voltage Vp and the rewrite voltage Vrwthemselves are not totally free from fluctuations, there may besituations where the voltage V1 becomes lower than the reference voltageVref or where the voltage V2 becomes greater than the reference voltageVref. In other words, errors in readout are likely to occur, adverselyaffecting the reliability. This is a second problem of prior artferroelectric memory devices.

In view of the first problem described above, there has been proposed amethod of using the ferroelectric capacitor 4 for an ordinary read/writein a first condition wherein the remanent polarization will not bechanged and for storing the memory content in a second condition whereinchanges in the remanent polarization are present (IEEE Electron DeviceLetters, Vol., 11, No. 10, October, 1990). This method may be effectiveagainst the problem regarding the useful endurance of the ferroelectriccapacitor, but it is not capable of improving the reliability bypreventing errors in readout. Moreover, this method requires two processalgorithms for the two conditions, making the process complicated. Itfurther requires a judging circuit for making a choice between the firstand second conditions, and the transition into the second condition inthe case of the occurrence of an abnormal condition may not take placesufficiently quickly. In summary, this method has problems also from thepoint of view of protecting stored data.

SUMMARY OF THE INVENTION

It is therefore an object of this invention to overcome the problems ofprior art ferroelectric memory devices using ferroelectric capacitors byproviding improved ferroelectric memory devices having a simplestructure and an improved useful endurance, which are reliable regardingreadout and other operations and protection of stored data, as well asmethods of storing data by using an improved ferroelectric memorydevice.

A ferroelectric memory device embodying this invention, with which theabove and other objects can be accomplished, may be characterized ascomprising a ferroelectric memory capacitor, a load capacitor, a readoutvoltage applying means, a memory content judging means and a rewritingmeans. The ferroelectric memory capacitor has a hysteresischaracteristic which defines a relationship between applied voltage andpolarization condition and is adapted to store selectively, based on itshysteresis characteristic, either a first memory content correspondingto a first polarization condition or a second memory contentcorresponding to a second polarization condition when there is noapplied voltage. The load capacitor is adapted to become electricallyconnected in series with the memory capacitor at least at a readout timeat which the content of the memory capacitor is read out. The readoutvoltage applying means is for applying a readout voltage to the seriesconnection of the memory capacitor and the load capacitor when thecontent of the memory capacitor is read out, or at the readout time. Thereadout voltage is characterized as having a polarity which is differentfrom the polarity of the voltage which will result in the firstpolarization condition. The memory content judging means is for judgingwhether the first memory content or the second memory content is storedin the memory capacitor, and this is done on the basis of the partialvoltage generated across the memory capacitor when the readout voltageis applied to it. The rewriting means is for applying a rewrite voltageto the memory capacitor for recovering the polarization conditioncorresponding to the memory content judged by the memory content judgingmeans. The readout voltage, the rewrite voltage to be applied forrecovering the first polarization condition (referred to herein as thefirst rewrite voltage), the hysteresis characteristic of the memorycapacitor and the characteristics of the load capacitor are adjustedsuch that the voltage across the memory capacitor, when the content ofthe memory capacitor is read out while the memory capacitor is in afully charged polarization condition by the first rewrite voltage forrecovering the first polarization condition, is zero or of the samepolarity as the first rewrite voltage.

According to another embodiment of the invention, a ferroelectriccapacitor having approximately the same characteristics as the memorycapacitor is used as the load capacitor, and the absolute value of thereadout voltage is adjusted to be smaller than or approximately the sameas the absolute value of the first rewrite voltage for recovering thefirst polarization condition.

At the time of a fast readout wherein the next readout takes placeimmediately after a rewrite, the ferroelectric memory capacitor does notchange its polarization condition from the first to the second, or thereis no change in the remanent polarization, and the useful endurance ofthe memory capacitor is not adversely affected.

Because the memory content is kept as remanent polarization,independently of whether it is a high-speed or low-speed readout, thereis no need for processes for saving or recalling a memory content.Neither is there any need for means for detecting a power shutdownbecause the memory content is not lost by a power shutdown. In summary,the present invention provides a memory device with a simple structurecapable of reliably storing memory contents and having an extendeduseful endurance.

Still another ferroelectric memory device according to this inventionmay be characterized as comprising, in addition to a ferroelectricmemory capacitor as described above, a ferroelectric referencecapacitor, a first load capacitor which is electrically connected inseries with the memory capacitor, and a second load capacitor which iselectrically connected in series with the reference capacitor. Both ofthese load capacitors are a ferroelectric capacitor having substantiallythe same characteristics as the memory capacitor. Let Vref denote thepartial voltage which appears across the reference capacitor if aspecified voltage is applied to the series connection of the referencecapacitor and the second load capacitor, and let V1 and V2 berespectively the partial voltage which appears across the memorycapacitor if the same specified voltage is applied to the seriesconnection of the memory capacitor and the first load capacitor when thememory capacitor is in the first or second polarization condition.According to this invention, the ratio of area between the referencecapacitor and the second load capacitor is such that Vref is nearlyequal to the average of V1 and V2 or slightly closer to V1 from thisaverage.

With a memory device thus structured, the values of the partial voltagesV1 and V2 are stable because the memory capacitor, the referencecapacitor and the two load capacitors have substantially the samecharacteristics. Since the capacitor areas are so adjusted that Vref isnearly equal to the average of V1 and V2 or slightly closer to V1 fromthis average, the device has a large margin or error in detecting thememory content. Variations in Vref corresponding to variations in thearea ratio are smaller if Vref is closer to V1. Thus, the inventionprovides an improved reliability associated with the readout.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part ofthis specification, illustrate embodiments of the invention and,together with the description, serve to explain the principles of theinvention. In the drawings:

FIG. 1 is a portion of a circuit diagram of a ferroelectric memorydevice according to a first embodiment of this invention usingferroelectric capacitors;

FIG. 2 is an enlarged circuit diagram of a portion of FIG. 1;

FIG. 3 shows the hysteresis characteristic of the memory capacitor C11of FIG. 2;

FIG. 4 is a hysteresis curve of a ferroelectric capacitor used in amemory device embodying this invention;

FIG. 5 is a hysteresis curve of another ferroelectric capacitor whichmay be used in a memory device of this invention;

FIG. 6 is a timing chart for the operation of the memory device of FIG.1 for reading out memory "H";

FIG. 7 is a timing chart for the operation of the memory device of FIG.1 for reading out memory "L";

FIG. 8 is a portion of a circuit diagram of ferroelectric memory devicesaccording to second and third embodiments of this invention;

FIG. 9 is a portion of the circuit diagram of FIG. 8 according to thesecond embodiment of this invention;

FIG. 10 shows the hysteresis characteristic of the memory capacitor C11incorporated in the memory device according to the second embodiment ofthe invention;

FIG. 11 is a portion of the circuit diagram of FIG. 8 according to thethird embodiment of the invention;

FIG. 12 shows the hysteresis characteristic of the memory capacitor C11of FIG. 11;

FIG. 13 shows hysteresis characteristics of the capacitors Ce and Cr ofFIG. 11;

FIGS. 14 and 15 show hysteresis characteristics of the capacitors Ce andCr as the ratio of their areas is changed;

FIG. 16 is a graph for showing the relationship between the area ratioof capacitors used in the memory device according to the thirdembodiment of this invention and reference voltage;

FIG. 17 is a timing chart for the operation of the memory deviceaccording to the third embodiment of this invention for reading outmemory "H";

FIG. 18 is a timing chart for the operation of the memory deviceaccording to the third embodiment of this invention for reading outmemory "L";

FIG. 19 is a circuit diagram of a portion of prior art ferroelectricmemory device; and

FIG. 20 is a hysteresis curve for showing the operation of aferroelectric capacitor used in a prior art memory device.

Throughout herein, components which are equivalent to each other,although being parts of different devices, are indicated by the samenumerals/symbols.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a portion of a circuit diagram of a ferroelectric memorydevice 10 (hereinafter referred to simply as "the memory device") usingferroelectric capacitors according to a first embodiment of thisinvention. The memory device 10 has a plurality of memory cells M11,M21, . . . Mmn in a matrix formation with rows and columns. In FIG. 1,the vertical arrays M11 . . . M1n and the horizontal arrays M11 . . .Mm1 are respectively referred to as columns and rows. The memory device10 also includes a reference cell drive circuit 12, a sense amplifiersection 14 having sense amplifiers AMP1, . . . and a reference cellpreset circuit 16. The reference cell driving circuit 12 may also bereferred to as the readout voltage applying means. The sense amplifiersection 14 and the reference cell preset circuit 16 may also be referredto as the memory content judging means. The reference cell driving means12 and the sense amplifier section 14 may also be referred to as therewrite means. It is to be noted that the reference cell drive circuit12 is used both in the readout voltage applying means and the rewritemeans, that the sense amplifier section 14 is used both in the memorycontent judging means and the rewrite means, and hence that the circuitstructure of this memory device 10 is simplified according to thisembodiment.

As shown in FIG. 2 which describes more in detail a portion of FIG. 1according to the first embodiment of this invention, the memory cell M11comprises a memory capacitor C11 serving as memory means (for storingdata) and a selection transistor TR11. One end of the memory capacitorC11 is electrically connected in series with a load capacitor Cb throughthe selection transistor TR11 and bit line /BL1. It is to be noted thatthe load capacitor Cb, in this example, is a paraelectric capacitorgiven as a parasitic capacitance between the bit line /BL1 and theground. The other end of the memory capacitor C11 is connected to thereference cell drive circuit 12 (shown in FIG. 1) through plate linePL1. The gate of the selection transistor TR11 is connected to word lineWL1. One end of sense amplifier AMP1 is connected to bit line /BL1, theother end of sense amplifier AMP1 being connected to the reference cellpreset circuit 16 through plate line PL1.

FIG. 3 shows the hysteresis characteristic of the memory capacitor C11,that is, the relationship between its voltage and polarizationcondition. The voltage is represented by that of the bit line /BL1 withthe plate line PL1 at reference voltage. The polarization condition isrepresented by the charge, which is its equivalent. With reference toFIG. 3, the condition with remanent polarization Z1 is referred to asthe first polarization condition P1 (corresponding to a first memorycontent "H"), and the condition with remanent polarization Z2 isreferred to as the second polarization condition P2 (corresponding to asecond memory content "L").

The electrostatic capacitance of the load capacitor Cb shown in FIG. 2is determined as follows. In FIG. 3, let Q1 be the point where thehorizontal line indicating the polarization condition P6 (correspondingto the first rewrite voltage Vrw1, to be described below) crosses thevertical line indicating the readout voltage Vp (to be described below).Consider a straight line which connects Q1 with the point P1,representing the first polarization condition on the hysteresis curve.The slope of this straight line represents the electrostatic capacitanceof the load capacitor Cb. As will be explained below, the remanentpolarization will hardly change when a memory content "H" is read out ata high speed if use is made of a load capacitor Cb with suchcapacitance, and adverse effects on the useful endurance can beprevented.

FIG. 4 shows the hysteresis H of the memory capacitor C11 in the circuitof FIG. 2. This may be considered as the synthesis of a ferroelectricterm Hf having a hysteresis characteristic and a paraelectric term Hphaving no hysteresis characteristic. Let R6 be the polarizationcondition based on the ferroelectric term Hf in the condition P6 when itis fully charged by a (first) rewrite voltage Vrw1 and R1 be thepolarization condition based on the ferroelectric term Hf in a firstpolarization condition P1. The hysteresis of the memory capacitor C11 isso determined that the polarization conditions R6 and R1 areapproximately the same. In other words, the memory capacitor C11 has ahigh susceptibility, that is, the ferroelectric term Hf has a steeprise. If a ferroelectric capacitor with such a hysteresis characteristicis used, there is hardly any variation in the polarization condition dueto the ferroelectric term Hf when the memory content "H" is read out ata fast rate, as will be explained below. This serves to prevent theshortening of the useful endurance.

If a ferroelectric capacitor with low susceptibility, as shown by FIG.5, is used, the difference (indicated by "d") between the polarizationconditions R6 and R1 becomes larger. If memory contents "H" are read outat a fast rate by using a ferroelectric capacitor having such ahysteresis characteristic, the change in the polarization condition dueto the ferroelectric term Hf is large, and this affects the usefulendurance adversely. In summary, it is preferred that the polarizationcondition R1 be at least greater than 80% of the polarization conditionR6.

Next, the operations for reading out a stored content from the memorydevice 10 will be explained with reference to FIGS. 1, 2, 3 and 6. Forreading out the content of memory cell M11, for example, thecorresponding address is inputted to the address buffer 18 shown in FIG.1, thereby selecting the target memory cell M11 through the columndecoder 20 for selecting a column and the row decoder 22 for selecting arow. Let us assume first that the memory capacitor C11 (of the memorycell M11) is in the polarization condition P6 of FIG. 6 (that is, fullycharged at first rewrite voltage Vrw1) when the (high-speed) readouttakes place. In this situation, the voltage on the bit line /BL1 shownin FIG. 2 is switched to "L" to thereby discharge the load capacitor Cb(as shown in FIG. 6 at (a)), and the bit line BL1 is then set in afloating condition (as shown in FIG. 6 at (b)). Next, the word line WL1is set to "H" to thereby set the selection transistor TR11 in the ONcondition (as shown in FIG. 6 at (c)), and then the plate line PL1 isset to "H" (as shown in FIG. 6 at (d)) according to an output from thereference cell drive circuit 12 (shown in FIG. 1). As the plate line PL1is set to "H", a readout voltage Vp is applied to both ends of thememory capacitor C11 and the load capacitor Cb, thereby causing apartial voltage V3 to be generated at the memory capacitor C11 as shownin FIG. 3. By analyzing on the graph, it is obtained that the partialvoltage V3 is given as the voltage on the memory capacitor C11 at thefirst polarization condition P1, or V3=0. In other words, the potentialof the bit line /BL1 with the ground as reference is of the value shownin FIG. 6 at (e).

Next, the sense amplifier AMP1 is activated (as shown in FIG. 6 at (f)).The sense amplifier AMP1 compares the reference voltage Vref (orthreshold voltage) shown in FIG. 3 provided from the reference cellpreset circuit 16 (shown in FIG. 1) through the bit line BL1 with thepartial voltage V3 of the memory capacitor C11 (although, in reality,the comparison is made between the potential of the reference voltageVref with respect to the readout voltage Vp shown in FIG. 3 with thepartial voltage V3). If the partial voltage V3 is higher, it isconcluded that the memory content is "H" and the voltage of the bit line/BL1 is set to "H" (as shown in FIG. 6 at (g)). The polarizationcondition of the memory capacitor C11 at this moment is P1. Thereference voltage Vref is set between partial voltages V1 and V2, aswill be explained below.

Next, the plate line PL1 is set to "L" in response to an output from thereference cell drive circuit 12 shown in FIG. 1 (as shown in FIG. 6 at(h)), causing a voltage difference between the plate line PL1 and thebit line /BL1 which is maintained at "H". This voltage difference servesas the first rewrite voltage Vrw1 shown in FIG. 3 applied to the memorycapacitor C11. The polarization condition of the memory capacitor C11 isnow P6 shown in FIG. 3, which is the fully charged condition.

Next, the word line WL1 is dropped to "L" (as shown in FIG. 6 at (i))while the memory capacitor C11 is in the fully charged condition by thefirst rewrite voltage Vrw1 such that the selection transistor TR11 isswitched to the OFF condition and the memory capacitor C11 is set in afloating condition. Next, the output line B1 of the row decoder 22(shown in FIG. 1) is raised (as shown in FIG. 6 at (j)) such that thevoltage level "H" of the bit line /BL1 (shown in FIG. 6 at (k)) is takeninto the output buffer 24 (as shown in FIG. 6 at (1)). The senseamplifier AMP1 is thereafter set to OFF condition (as shown in FIG. 6 at(m)) such that the bit line /BL1 is again set in a floating condition(as shown in FIG. 6 at (n)). Finally, the output line B1 of the rowdecoder 22 is returned to "L" and the readout process is completed.

In the case of such a high-speed readout, that is, in the case of areadout with a short cycle such that the next readout takes place afterthe memory capacitor C11 is fully charged by the first rewrite voltageVrw1 but before it is discharged, the polarization condition of thememory capacitor C11 changes only from P6 to P1 to P6 during the courseof the process as described above. As a result, the remanentpolarization of the memory capacitor C11 remains at the firstpolarization condition P1 and does not change. In other words, theuseful endurance of the memory capacitor C11 is not adversely affectedby the change in remanent polarization at the time of a high-speedreadout. As shown in FIG. 4, furthermore, there is hardly any change inthe polarization condition due to the ferroelectric term Hf during thecourse of changes in the polarization condition of the memory capacitorC11 from P6 to P1 to P6. According to this embodiment of the invention,therefore, neither is there hardly any adverse effect on the usefulendurance of the memory capacitor C11 due to the changes in polarizationcondition based on the ferroelectric terms Hf.

Next will be explained the operations at the time of readout at a longcycle, that is, when the (low-speed) readout is carried out when theparaelectric term Hp (shown in FIG. 4) is completely discharged, thatis, at the first polarization condition P1 shown in FIG. 3.

The memory device 10 according to this embodiment of the inventioncarries out readouts entirely in the same ways, without distinguishingbetween high-speed and low-speed readouts. In other words, a low-speedreadout is carried out in the same way as the high-speed readout. In thecase of a low-speed readout, however, it is different in that thereadout takes place when the polarization condition is P1, as shown inFIG. 3, not P6 as in the case of a high-speed readout. Thus, thepolarization condition of the memory capacitor C11 is P4 when a readoutvoltage Vp is applied as shown in FIG. 3 in the case of a slow-speedreadout, and the partial voltage generated at the memory capacitor C11is V1 . The voltage of the bit line /BL1 with respect to the ground atthis moment is as shown in FIG. 6 at (e'). Since the reference voltageVref is set to be lower than V1 , as explained above, the senseamplifier AMP1 concludes that the memory content is "H" as in the caseof a high-speed readout and sets the potential of the bit line /BL1 tobe "H" (as shown in FIG. 6 at (g)). The polarization condition of thememory capacitor C11 at this moment is P5, as shown in FIG. 3.

A rewrite is thereafter carried out by applying the first rewritevoltage Vrw1 (as shown in FIG. 6 at (h)) to the memory capacitor C11.The polarization condition of the memory capacitor C11 becomes P6 bythis rewrite. After the readout operations, the charges based on theparaelectric term Hp (shown in FIG. 4) of the memory capacitor C11 arecompletely discharged as time elapses, and the polarization conditionreturns to P1.

In summary, the remanent polarization changes from P1 to P5 to P1 in thecase of a low-speed readout, and as the polarization condition of thememory capacitor C11 changes from P1 to P4, as shown in FIG. 4, thepolarization condition based on the ferroelectric term Hf also changesfrom R1 to R4. Thus, the useful endurance of the memory capacitor C11will be adversely affected when the memory content "H" is read out at alow speed. When the readout is at a low speed, however, the number ofreadout operations per unit time is small, and since the effect on theuseful endurance per unit time is also small, this does not amount to aserious problem.

Next will be explained the operations for reading out a memory content"L" with reference to the timing chart in FIG. 7. As can be understoodby comparing FIGS. 6 and 7, the memory device 10 according to thisembodiment of the invention does not distinguish between reading out "H"and "L" and follows the same steps for the readout. In other words, thereadout of "L" is carried out exactly like that of "H" except that, inthe case of reading out "L", the polarization condition at the time ofthe readout is P2. It is also different from the readout of "H" in thatthe polarization condition at the time of the readout is always P2whether it is high-speed readout or low-speed readout.

When a memory content "L" is read out, the polarization condition of thememory capacitor C11 becomes P3 if the readout voltage Vp shown in FIG.3 is applied. Accordingly, the partial voltage at the memory capacitorC11 is V2. At the moment, the potential of the bit line /BL1 is as shownin FIG. 7 at (a) with reference to the ground. Since the referencevoltage Vref is set to be higher than V2, as explained above, the senseamplifier AMP1 concludes that the memory content is "L" and sets thevoltage of the bit line /BL1 at "L" (as shown in FIG. 7 at (b)).

As the bit line /BL1 is set at "L", there appears a potential differencebetween the bit line /BL1 and the plate line PL1 kept at "H". Thispotential difference serves as the second rewrite voltage Vrw2 (which isequal to the readout voltage Vp) which is applied to the memorycapacitor C11. With the second rewrite voltage Vrw2 thus applied, thepolarization condition of the memory capacitor C11 becomes P7 as shownin FIG. 3.

The plate line PL1 is then set to "L" (as shown in FIG. 7 at (c)). Thisforcibly makes the voltage across the memory capacitor C11 to zero, andthe charges based on the paraelectric term Hp of the memory capacitorC11 as shown in FIG. 4 are forcibly discharged and the polarizationcondition returns to P2 shown in FIG. 3.

In summary, during the series of processes for reading a memory contentof "L", the polarization condition of the memory capacitor C11 changesonly from P2 to P3 to P7 to P2. Thus, the remanent polarization of thememory capacitor C11 remains P2 and does not vary. According to thisembodiment of the invention, therefore, there is no shortening of theuseful endurance of the memory capacitor C11 due to variations in theremanent polarization for reading out "L".

As shown in FIG. 4, furthermore, there is hardly any change in thepolarization condition based on the ferroelectric term Hf during thecourse of changes in the polarization condition of the memory capacitorC11 from P2 to P3 to P7 to P2. Thus, neither is there hardly anyshortening of the useful endurance of the memory capacitor C11 due tovariations in the polarization condition based on the ferroelectric termHf.

According to this embodiment of the invention, therefore, the usefulendurance of the memory capacitor C11 is adversely affected only forreading out a memory content "H" at a low speed. When the readout iscarried out at a low speed, however, the lowering of the endurance perunit time is small, as discussed above, and hence it does not become apractical problem. Moreover, readout can be carried out by the sameprocedure, independent of whether the readout cycle is long or short andwhatever the content of memory.

Although the first embodiment of this invention was described above withreference to one particular example, many modifications and variationsare still possible. For example, although parasitic capacitance of bitline was used as the load capacitor Cb in the above example, a separatecapacitor may be utilized. Although a paraelectric capacitor was used asthe load capacitor Cb, a capacitor of a different type may be usedinstead.

The capacitance of the load capacitor Cb need not be determined suchthat the voltage on the memory capacitor C11 be approximately zero atthe time of a readout while the memory capacitor C11 is fully charged bythe first rewrite voltage Vrw1. The capacitance of the load capacitor Cbmay be determined such that the voltage on the memory capacitor C11 beof the same polarity as the first rewrite voltage Vrw1. Moreover,adjustments may be made on one or more from the readout voltage Vp, thefirst rewrite voltage Vrw1 and the hysteresis characteristic of theferroelectric capacitor. Adjustments may likewise be made on thecapacitance of the load capacitor and one or more of these elements.

Similarly, the readout voltage Vp and the second rewrite voltage Vrw2were made equal in the example above but they may be different.

The hysteresis characteristic of the memory capacitor C11 may be, butneed not be such that the polarization condition R6 based on theferroelectric term Hf under the fully charged condition P6 by the firstrewrite voltage Vrw1 and the polarization condition R1 based on theferroelectric term Hf under the first polarization condition P1 areapproximately equal. Neither is the readout procedure for the memorydevice 10 limited by the timing charts in FIGS. 6 and 7, and the circuitstructure shown in FIG. 1 is not intended to limit the scope of thefirst embodiment of the invention.

Another ferroelectric memory device 10' according to a second embodimentof this invention is described next with reference to FIGS. 8 and 9wherein components which are identical or substantially similar to thoseexplained above with reference to the first embodiment of the inventionare indicated by the same numerals or symbols for convenience and willnot be explained repetitively especially since FIGS. 8 and 9 are verymuch similar to FIGS. 1 and 2, respectively.

In FIGS. 8 and 9, the load capacitor Cb is a ferroelectric capacitorformed on the same substrate as the ferroelectric memory capacitor C11in the same production process, having the same characteristics suchthat it can be assured that they have the same characteristics even ifthere were fluctuations in the conditions of their production, and thissignificantly improves the reliability of their operations. In thisexample, furthermore, the first rewrite voltage Vrw1 and the readoutvoltage Vp (to be explained below) are set such that their absolutevalues are the same. As a result, the voltage on the memory capacitorC11 becomes approximately zero at the time of a readout by the firstrewrite voltage Vrw1 when the memory capacitor C11 is in a fully chargedpolarization condition. Thus, there is hardly any variation in theremanent polarization when a memory content "H" is read out, and adverseeffects on the useful endurance of the capacitor can be prevented.

The hysteresis characteristic H of the memory capacitor C11 in thecircuit of FIG. 9 is also shown by FIG. 4. As explained above withreference to FIGS. 5, 6 and 7 for the first embodiment of thisinvention, the useful endurance of such a memory capacitor C11 is notadversely affected by changes in remanent polarization. According thethis embodiment of the invention, as shown in FIG. 8, one end of theferroelectric load capacitor Cb is grounded, the other end beingconnected to the bit line /BL1. As shown in FIGS. 6 and 7, the potentialon the bit line /BL1 fluctuates only between "H" (corresponding to thefirst rewrite voltage Vrw1) and "L" (corresponding to ground potential).Thus, the voltage applied to the load capacitor Cb is always in the samedirection and its magnitude is within the range of 0-Vrw1. For thisreason, there is no inversion of polarization in this ferroelectric loadcapacitor Cb during the processes described above. In other words, evenif the load capacitor Cb is a ferroelectric capacitor, the usefulendurance of memory capacitor C11 is not adversely affected by thepolarization inversion of the load capacitor Cb. According to apreferred embodiment, the memory capacitor C11 and the load capacitor Cbare formed on the same substrate in the same production step at the sametime such that fluctuations at the production steps can be absorbed andreliability of the products can be improved, independent of the lengthof the readout cycle or the content of the memory being read out,although this is not intended to limit the scope of the secondembodiment of the invention. The second embodiment is characterized onlyin that the load capacitor be a ferroelectric capacitor havingsubstantially the same characteristics as the ferroelectric memorycapacitor C11. The first rewrite voltage Vrw1 and the readout voltage Vpmay be such that their absolute values are the same, or the absolutevalue of the readout voltage Vp may be made smaller than the absolutevalue of the first rewrite voltage Vrw1. Similarly, the readout voltageVp and the second rewrite voltage Vrw2 were of the same value in theabove example but they are not required to be of the same value.Likewise, the hysteresis characteristic of the ferroelectric loadcapacitor C11 need not be selected such that the polarization conditionR6 based on the ferroelectric term Hf at the condition P6 fully chargedby the first rewrite voltage Vrw1 be the same as the polarizationcondition R1 based on the ferroelectric term Hf at the firstpolarization condition P1.

Still another ferroelectric memory device according to a thirdembodiment of this invention is described next with reference to FIGS. 8and 11 wherein components which are identical or substantially similarto those explained above with reference to the first and secondembodiments of the invention are indicated by the same numerals orsymbols for convenience and will not be explained repetitively. Thereference cell driving circuit 12 of FIG. 8 serves as the readout andthreshold voltage generating and applying means. The sense amplifiersection 14 and the reference cell preset circuit 16 serve as the memorycontent judging means.

As shown more in detail in FIG. 11, the memory cell M11 comprises aferroelectric memory capacitor C11 serving as memory means (for storingdata) and a selection transistor TR11. One end of the memory capacitorC11 is electrically connected in series with a load capacitor Cb(hereinafter referred to as "the first load capacitor") through theselection transistor TR11 and a bit line /BL1. The other end of thememory capacitor C11 is connected to the reference cell drive circuit 12(shown in FIG. 8) through plate line PL1. The gate of the selectiontransistor TR11 is connected to word line WL1. One end of senseamplifier AMP1 is connected to bit line /BL1, the other end of senseamplifier AMP1 being connected to the reference cell preset circuit 16through bit line BL1.

In the reference cell preset circuit 16, one end of ferroelectriccapacitor Cr for reference is electrically connected in series withanother load capacitor Cc (hereinafter referred to as "the second loadcapacitor") through transistor TRC and bit line BL1. It is alsoconnected to grounding line VSS through transistor TRD. The other end ofthe ferroelectric capacitor Cr is connected to the reference cell drivecircuit 12 (shown in FIG. 8) through plate line GCP. The gate of thetransistor TRC is connected to the reference cell drive circuit 12through line RWL. The gate of the transistor TRD is connected to thereference cell drive circuit 12 through line RBP. Bit lines /BL1 and BL1are connected to the grounding line VSS respectively through transistorsTRA and TRB. The gates of the transistors TRA and TRB are both connectedto a bit line equalize circuit 13 (shown in FIG. 8).

FIG. 12 shows the hysteresis characteristic of the memory capacitor C11of FIG. 11, that is, the relationship between its voltage andpolarization condition. The voltage is represented by that of the bitline /BL1 with the plate line PL1 at reference voltage. The polarizationcondition is represented by the charge, which is its equivalent. Withreference to FIG. 12, the condition with remanent polarization Z1 isagain referred to as the first polarization condition P1 (correspondingto a first memory content "H"), and the condition with remanentpolarization Z2 is similarly referred to as the second polarizationcondition P2 (corresponding to a second memory content "L").

According to an example shown in FIG. 11, the first rewrite voltage Vrw1and the readout voltage Vp (to be explained below) are set such thattheir absolute values are equal. If they are thus set, the voltagegenerated across the memory capacitor C11 becomes nearly zero at thetime of a readout by the first rewrite voltage Vrw1 when the memorycapacitor C11 is in the fully charged polarization condition. As aresult, there will be hardly any variation in the remanent polarizationin the memory capacitor C11 at the time of reading out a memory content"H" at a high speed, and this serves to prevent adverse effects on theuseful endurance of the capacitor.

The hysteresis H shown in FIG. 4 of the memory capacitor C11 of FIG. 11is also considered as the synthesis of a ferroelectric term Hf having ahysteresis characteristic and a paraelectric term Hp having nohysteresis characteristic. Let R6 be the polarization condition based onthe ferroelectric term Hf in the condition P6 when it is fully chargedby a (first) rewrite voltage Vrw1 and R1 be the polarization conditionbased on the ferroelectric term Hf in a first polarization condition P1.The hysteresis of the memory capacitor C11 is so determined that thepolarization conditions R6 and R1 are approximately the same. In otherwords, the memory capacitor C11 has a high susceptibility, that is, theferroelectric term Hf having a steep rise. If a ferroelectric capacitorwith such a hysteresis characteristic is used, there is hardly anyvariation in the polarization condition due to the ferroelectric term Hfwhen the memory content "H" is read out at a fast rate, as will beexplained below. This serves to prevent the shortening of the usefulendurance.

If a ferroelectric capacitor with low susceptibility, as shown by FIG.5, is used, the difference (indicated by "d") between the polarizationconditions R6 and R1 becomes larger. Thus, if memory contents "H" areread out at a fast rate from a ferroelectric capacitor with such ahysteresis characteristic, the change in the polarization condition dueto the ferroelectric term Hf is large, and this affects the usefulendurance adversely. In summary, it is preferred that the polarizationcondition R1 based on the ferroelectric term Hf at the firstpolarization condition P1 be at least greater than 80% of thepolarization condition R6 based on the ferroelectric term Hf atcompletely charged condition P6 by the first rewrite voltage Vrw1.

FIG. 13 shows the hysteresis curve of the ferroelectric capacitor Crrelating the voltage (or the potential of the bit line BL1 when theplate line GCP is taken as reference potential with reference to FIG.11) and its polarization condition (represented by the equivalentcharge). According to a preferred embodiment of the invention, thecapacitors Cr, Cc, C11 and Cb are all formed on the same substrate andfabricated at the same time such that, even if there were fluctuationsduring their production processes, these fluctuations are mutuallycompensated for such that variations associated with such fluctuationsduring their production will have no significant effect. The capacitorsC11, Cb and Cc are preferably designed such that they have approximatelythe same hysteresis characteristics such that they are guaranteed tohave the same characteristics and the reliability of their functions isimproved.

FIG. 13 shows, however, the capacitors Cr and Cc as not having the samehysteresis characteristics. The reference voltage Vref can be determinedby combining the hysteresis characteristics of these two capacitors, aswill be described below. FIG. 13 shows a combination wherein the area(the effective area of mutually opposite electrode plates) of theferroelectric capacitor Cr is about 1.7 times as large as that of theload capacitor Cc. In the example of FIG. 13, the reference voltage Vrefwith respect to the ground potential is about 3.6 V (about -1.6 V withrespect to the potential of the plate line PL1).

If the ratio of the area of the ferroelectric capacitor Cr is increased,the reference voltage Vref is also increased as shown in FIG. 14. Ifthis ratio is reduced, on the other hand, the reference voltage Vrefalso becomes smaller as shown in FIG. 15. FIG. 16 shows the relationshipbetween the ratio of area and the reference voltage Vref, indicating howthe reference voltage Vref increases as the ratio of the area of theferroelectric capacitor Cr is increased. According to the illustratedexample, the reference voltage Vref becomes the average of the partialvoltages V1 and V2 with respect to the ground potential (to be explainedbelow) if the area ratio is about 1.4, increasing the margin ofdetection when reading out the memory content (also to be explained indetail below).

It is noted that the curve shown in FIG. 16 is convex to the top. Thus,the change in the reference voltage Vref corresponding to a change inthe area ratio becomes smaller as the reference voltage Vref approachesthe partial voltage V1 (or as the area ratio becomes larger). In otherwords, the reference voltage Vref should be made larger in order toreduce the variations in the reference voltage Vref caused by thefluctuations in the area ratio. It is preferable to set the referencevoltage Vref close to the average of V1 and V2 or somewhat closer to V1.If it is so set, a safety margin of detection can be maintained whenreading out a memory content even if the fluctuation in the area ratiois large due to the production process. According to the illustratedexample, the area ratio is about 1.7, and FIG. 16 shows that there willbe no readout error if the variations in the area ratio are by less thanabout ±0.6.

Next will be explained the operations for reading out the memory contentfrom the memory device of FIGS. 8 and 11. For reading out the memorycontent of the memory cell M11 shown in FIG. 11, its address is firstinputted to the address buffer 18 such that the memory cell M11 will beselected through a column decoder 20 for selecting a column and a rowdecoder 22 for selecting a row.

Operations for reading out a memory content "H" will be described nextwith reference to the timing chart in FIG. 17 together with FIGS. 8, 11,12 and 13. A situation of high-speed readout whereby the readout takesplace when the memory capacitor C11 is in the fully charged polarizationcondition P6 (as shown in FIG. 12) by the first rewrite voltage Vrw1 (tobe explained below) will be explained.

First, the bit line equalize circuit 13 (shown in FIG. 8) holds the lineBP at "H" for a specified length of time and then returns it to "L" (asshown in FIG. 17 at (a)). Transistors TRA and TRB (shown in FIG. 11) arethereby switched on for a while, connecting the grounding line VSS tobit lines /BL1 and BL1 and setting the bit lines /BL1 and BL1 to "L" (asshown in FIG. 17 at (b) and (c)). As the bit lines /BL1 and BL1 are keptat "L" for a specified length of time, the load capacitors Cb and Cc aredischarged. Thereafter, the transistors TRA and TRB are switched off andthe bit lines /BL1 and BL1 are set in a floating condition (as shown inFIG. 17 at (d) and (e)).

As the line BP is kept at "H" for a specified length of time, line RBPshown in FIG. 11 is simultaneously kept at "H" by the reference celldrive circuit 12 (shown in FIG. 8) and then returned to "L" (as shown inFIG. 17 at (y)). As a result, transistor TRD is switched on for a while,connecting one end of the ferroelectric capacitor Cr with the groundingline VSS and setting it to "L". The plate line GCP to which the otherend of the ferroelectric capacitor Cr is connected is at "L" at thismoment (as shown in FIG. 17 at (z)). Thus, the ferroelectric capacitorCr is forcibly put in the polarization condition P11 as shown in FIG.13, independent of its earlier polarization condition.

Next, the reference cell drive circuit 12 sets the plate lines PL1 andGCP to "H" (as shown in FIG. 17 at (f) and (g)) such that a high voltage"H" (corresponding to the readout voltage Vp and the thresholdgenerating voltage Vr) is applied to the other ends of the ferroelectriccapacitors C11 and Cr.

Next, the word line WL1 is set to "H" (as shown in FIG. 17 at (h)) suchthat the selection transistor TR11 is switched on, electricallyconnecting the memory capacitor C11 and the load capacitor Cb in series.This means that the readout voltage Vp is now applied to the ends of thememory capacitor C11 and the load capacitor Cb which are connectedtogether, generating a partial voltage V3 across the memory capacitorC11. According to an analysis from the graph, the partial voltage V3 maybe given as the voltage of the memory capacitor C11 at the firstpolarization condition P1, or V3=0. The potential of the bit line /BL1with respect to the ground is as shown in FIG. 17 at (i).

As the word line WL1 is set to "H" as described above, the line RWL isset to "H" by the reference cell drive circuit 12 (as shown in FIG. 17at (j)), thereby switching on the transistor TRC and electricallyconnecting the memory capacitor C11 and the load capacitor Cc in series.Thus, a threshold generating voltage Vr (equal to the readout voltage Vpin this example) is applied to the ends of the memory capacitor C11 andthe load capacitor Cc which are connected together.

As explained above, the ferroelectric capacitor Cr is in polarizationcondition P11 shown in FIG. 13 immediately before it is connected. Thus,a partial voltage (reference voltage Vref) based on the thresholdgenerating voltage Vr is generated across the ferroelectric capacitor Cras it is connected with the load capacitor Cc. By analyzing FIG. 13, thereference voltage Vref is given as the voltage of the ferroelectriccapacitor Cr in the polarization condition P12. Accordingly, thepotential of the bit line BL1 with respect to the ground becomes asshown in FIG. 17 at (k).

Next, the sense amplifier AMP1 is activated (as shown in FIG. 17 at(1)). The sense amplifier AMP serves to compare the reference voltageVref (threshold voltage) provided by the reference cell preset circuit16 through the bit line BL1 and the partial voltage V3 (described above)of the memory capacitor C11 (that is, the potential of reference voltageVref with respect to the readout voltage Vp shown in FIG. 12 and thepotential of the partial voltage V3). If the partial voltage V3 ishigher, it is concluded that the memory content is "H", setting thepotential of the bit line /BL1 to "H" (as shown in FIG. 17 at (m)) andthe potential of the bit line BL1 to "L" (as shown in FIG. 17 at (n)).At this moment, the polarization condition of the memory capacitor C11remains at P1 shown in FIG. 12. The polarization condition of theferroelectric capacitor Cr is P13 as shown in FIG. 13.

Next, the line RWL is set to "L" according to an output from thereference cell drive circuit 12 (shown in FIG. 8) (as shown in FIG. 17at (o)), setting the ferroelectric capacitor Cr in a floating condition.Thus, with the elapse of time thereafter, the ferroelectric capacitor Crapproaches the polarization condition P11 shown in FIG. 13 throughnatural discharge.

Next, the plate lines PL1 and GCP are set to "L" (as shown in FIG. 17 at(p) and (q)) according to an output from the reference cell drivecircuit 12 (shown in FIG. 8). As the plate line PL1 is set to "L", thereappears a potential difference between the plate line PL1 and the bitline /BL1 maintained at "H". This potential difference represents thefirst rewrite voltage Vrw1 shown in FIG. 12 applied across the memorycapacitor C11. The polarization condition of the memory capacitor C11thereby becomes P6, shown in FIG. 12, which is a fully chargedcondition. Since the ferroelectric capacitor Cr is in a floatingcondition, as explained above, there is no change in the polarizationcondition of the ferroelectric capacitor Cr as the plate line GCP is setto "L".

Next, the word line WL1 is dropped to "L" (as shown in FIG. 17 at (r))while the memory capacitor C11 is in the fully charged condition by thefirst rewrite voltage Vrw1 so as to switch off the selection transistorTR11 and set the memory capacitor C11 in a floating condition.

Next, the output line B1 (shown in FIG. 8) of the row decoder 22 israised (as shown in FIG. 17 at (s)) to take the potential level "H" ofthe bit line /BL1 (as shown in FIG. 17 at (t)) into the output buffer24. The sense amplifier AMP1 is thereafter switched off (as shown inFIG. 17 at (u)) to set the bit lines /BL1 and BL1 in a floatingcondition again (as shown in FIG. 17 at (v) and (w)). Finally, theoutput line B1 of the row decoder 22 is returned to "L" (as shown inFIG. 17 at (x)) to complete the readout process.

In such a case of high-speed readout with a short cycle, wherein thenext readout takes place after the memory capacitor C11 is fully chargedby the rewrite voltage Vrw1 and before it is discharge, the polarizationcondition of the memory capacitor C11 changes only from P6 to P1 to P6during the course of readout processes described above. As a result, theremanent polarization of the memory capacitor C11 remains in the firstpolarization condition P1 and does not change. In this example,therefore, the useful endurance of the memory capacitor C11 will not beadversely affected by variations in the polarization condition at thetime of high-speed readout.

As shown in FIG. 4, furthermore, neither is there hardly any variationin the polarization condition based on the ferroelectric term Hf whilethe polarization condition of the memory capacitor C11 changes from P6to P1 to P6. In this example, therefore, there is hardly any adverseeffect on the useful endurance of the memory capacitor C11 due to thevariations in the polarization condition based on the ferroelectric termHf.

As described above, the polarization condition of the ferroelectriccapacitor Cr changes only from P11 to P12 to P13 (and to P11) during theseries of readout processes. Thus, the remanent polarization of theferroelectric capacitor Cr remains P11 and does not vary. In thisexample, therefore, there is no adverse effect on the useful enduranceof the ferroelectric capacitor Cr due to variations in the remanentpolarization during a high-speed readout.

Next will be explained the processes of slowspeed readout at a longcycle wherein the readout takes place when the paraelectric term Hp ofthe memory capacitor C11 (as shown in FIG. 4) is in the totallydischarged condition, or in the first polarization condition P1.

The memory device according to this embodiment carries out readouts bythe same processes, without distinguishing whether it is a high-speedreadout or a low-speed readout. In other words, a low-speed readout iscarried out by the same procedure as the high-speed readout. As aresult, the reference voltage Vref is the same as in the case ofhigh-speed readout described above. In the case of low-speed readout,however, the polarization condition of the memory capacitor C11 at thetime of a readout is the first polarization condition P1, as shown inFIG. 12, not P6 as in the highspeed readout, and this is the onlydifference.

Accordingly, when the readout voltage Vp shown in FIG. 12 is applied atthe time of a low-speed readout, the polarization condition of thememory capacitor C11 is P4, and the partial voltage across the memorycapacitor C11 is V1. The potential of the bit line /BL1 at this momentwith reference to the ground is as shown in FIG. 17 at (i'). Since thereference voltage Vref is set below V1 as described above, however, thesense amplifier AMP1 concludes, as in the case of highspeed readout,that the memory content is "H", setting the bit line /BL1 at "H" (asshown in FIG. 17 at (m)) and the bit line BL1 at "L" (as shown in FIG.17 at (n)). At this moment, the polarization condition of the memorycapacitor C11 is P5, as shown in FIG. 12.

A rewrite is carried out thereafter by applying the first rewritevoltage Vrw1 across the memory capacitor C11 (as shown in FIG. 17 at(p)). The polarization condition of the memory capacitor C11 therebybecomes P6. After the readout is completed, the charges based on theparaelectric term Hp shown in FIG. 4 of the memory capacitor C11 arecompletely discharged with time and the first polarization condition P1shown in FIG. 12 is reached.

Thus, the remanent polarization varies from P1 to P5 to P1 at the timeof a slow-speed readout and, as the polarization condition of the memorycapacitor C11 changes from P1 to P4, the polarization condition based onthe ferroelectric term Hf also changes from R1 to R4. Thus, there willbe shortening of the useful endurance of the memory capacitor C11 whenreading out "H" at a low speed. When the readout is at a slow speed,however, this does not become a problem because the number of readoutsper unit time is small and hence the shortening of the endurance perunit time is also small.

The operations by the ferroelectric capacitor Cr are the same as in thecase of high-speed readout. Thus, the remanent polarization of theferroelectric capacitor Cr is P11 and does not change even in the caseof low-speed operation, and there is no adverse effect on the usefulendurance due to variations in remanent polarization at the time oflow-speed readout.

Next will be explained the operations for reading out a memory content"L". As shown in FIGS. 17 and 18, the memory device 10' according tothis invention are adapted to function identically for a readout withoutdistinguishing whether it is reading out a memory content "H" or "L". Inother words, the readout of a memory content "L" is carried out as thatof a memory content "H". In the case of reading out "L", however, thememory capacitor C11 is in the second polarization condition P2 at thetime of readout. In this example, it is so adapted that the polarizationcondition will be always P2 when reading out a memory content "L"whether by high-speed readout or slow-speed readout.

When the readout voltage Vp shown in FIG. 12 is applied for reading amemory content "L", the memory capacitor C11 shows the polarizationcondition of P3, and its partial voltage is V2. At this moment, thepotential of the bit line /BL1 with respect to the ground is as shown inFIG. 18 at (a). On the other hand, the potential of the bit line BL1becomes the same as the reference voltage Vref as in the case of memorycontent "H" (as shown in FIG. 18 at (b)) but, since the referencevoltage Vref is set at a level higher than V2, the sense amplifier AMP1concludes that the memory content is "L" and sets the potential of thebit line /BL1 to "L" (as shown in FIG. 18 at (c)) and the potential ofthe bit line BL1 to "H" (as shown in FIG. 18 at (d)).

As the potential of the bit line /BL1 is set at "L", a potentialdifference is generated between the bit line /BL1 and the plate line PL1maintained at "H". This potential difference is the second rewritevoltage Vrw2 (equal to the readout voltage Vp) which is applied to thememory capacitor C11. When the second rewrite voltage Vrw2 is applied,the polarization condition of the memory capacitor C11 becomes P7.

As the potential of the bit line BL1 is set at "H", however, therearises no potential difference between the bit line BL1 and the plateline GCP maintained at "H". In other words, the voltage across thememory capacitor C11 is zero and the polarization condition of theferroelectric capacitor Cr is forcibly returned from P12 to P11 as shownin FIG. 13.

The plate line PL1 is thereafter set to "L"(as shown in FIG. 18 at (e))to forcibly set the voltage on the memory capacitor C11 equal to zero.As a result, the charges based on the paraelectric term Hp (shown inFIG. 4) of the memory capacitor C11 become completely discharged and thesecond polarization condition P2 shown in FIG. 12 is reached.

In summary, the polarization condition of the memory capacitor C11changes only from P2 to P3 to P7 to P2 during the series of readoutoperations for reading out a memory content "L" as shown in FIG. 12.Thus, the remanent potential of the memory capacitor C11 remains at thesecond polarization condition P2 without changing. Therefore, the usefulendurance of the memory capacitor C11 is not adversely affected due tothe variations in remanent potential for reading out memory content "L".Neither is there hardly any variation in the polarization conditionbased on the ferroelectric term Hf while the polarization condition ofthe memory capacitor C11 changes from P2 to P3 to P7 to P2, as shown inFIG. 4. Accordingly, neither is there hardly any adverse effect on theuseful endurance of the memory capacitor C11 due to variations in thepolarization condition based on the ferroelectric term Hf for readingmemory content "L".

As for the ferroelectric capacitor Cr, its polarization conditionchanges only from P11 to P12 to P11, as shown in FIG. 13. Thus, itsremanent polarization remains at P11, without undergoing any variations.In other words, there is no shortening in the useful endurance due tothe variation in the remanent polarization for reading memory content"L".

In summary, the useful endurance of the memory capacitor C11 isadversely affected only when reading out memory content "H" at a lowspeed, but the low-speed reading does not present any serious problembecause the lowering of the useful endurance per unit time isinsignificant in the case of a low-speed readout. Moreover, there is noadverse effect on the useful endurance of the ferroelectric capacitor Crwhether the memory content is "H" or "L", as described above.

As shown in FIG. 11, furthermore, one end of the load capacitor Cb isgrounded and the other end is connected to the bit line /BL1, while, asshown in FIGS. 17 and 18, the potential of the bit line moves onlybetween "H" (corresponding to the first rewrite voltage Vrw1) and "L"(corresponding to the ground potential) during each operation describedabove. Thus, the voltage applied across the load capacitor Cb is alwaysin the same direction, changing between zero and Vrw1, causing noinversion of polarization during the various operations described above.In summary, although the load capacitor Cb comprises a ferroelectricmaterial in this example, its useful endurance is not adversely affecteddue to the inversion of polarization. The same is also true with theload capacitor Cc.

If all capacitors C11, Cr, Cb and Cc are formed on the same substrate ina same production process, the fluctuations at the time of fabricationcan be absorbed, and the reliability of the product can be improved.Another advantage is that readout can be effected by the same processwhether the readout cycle is long or short and independent of the memorycontent.

Although the third embodiment of the invention was described above withreference to an example (as shown in FIGS. 13 and 16) wherein the arearatio between the capacitors Cr and Cc is about 1.7, the area ratio isnot limited to this value but may be selected such that the referencevoltage Vref will be near the average value of partial voltages V1 andV2 or somewhat closer to V1.

Although many preferred conditions have been mentioned throughoutherein, they are not intended to limit the scope of the invention. Forexample, the capacitors C11, Cr, Cb and Cc need not necessarily be seton the same substrate or produced in a same production step. Theabsolute values of the first rewrite voltage Vrw1 and the readoutvoltage Vp need not be the same. Similarly, the readout voltage Vp andthe second rewrite voltage Vrw2 need not necessarily be set equal toeach other, and the readout voltage Vp need not necessarily be set equalto the threshold generating voltage Vr. Moreover, the hysteresischaracteristic of the memory capacitor C11 need not necessarily beselected such that the polarization condition R6 based on theferroelectric term Hf at the fully discharged condition P6 by the firstrewrite voltage Vrw1 should be about equal to the polarization conditionR1 based on the ferroelectric term Hf at the first polarizationcondition P1. Neither the timing charts in FIGS. 17 and 18 nor even thestructure of the memory device itself is intended to limit the scope ofthe invention. All modifications and variations of the description givenabove, which may be apparent to a person skilled in the art, areintended to be within the scope of this invention.

What is claimed is:
 1. A ferroelectric memory device comprising:aferroelectric memory capacitor having a hysteresis characteristicdefining a relationship between applied voltage and polarizationcondition, said memory capacitor being adapted to store selectively,based on said hysteresis characteristic, either a first memory contentcorresponding to a first polarization condition or a second memorycontent corresponding to a second polarization condition when appliedvoltage is zero; a first load capacitor which is electrically connectedin series with said memory capacitor; a ferroelectric referencecapacitor; and a second load capacitor which is electrically connectedin series with said reference capacitor, said first and second loadcapacitors being each a ferroelectric capacitor having substantiallysame characteristics as said memory capacitor; wherein the ratio of areabetween said reference capacitor and said second load capacitor is suchthat Vref is nearly equal to the average of V1 and V2 or slightly closerto V1 from said average, where Vref is the partial voltage which appearsacross said reference capacitor if a specified voltage is applied tosaid reference capacitor and said second load capacitor connected toeach other in series, where V1 is the partial voltage which appearsacross said memory capacitor if said specified voltage is applied tosaid memory capacitor and said first load capacitor connected to eachother in series when said memory capacitor is in said first polarizationcondition, and where V2 is the partial voltage which appears across saidmemory capacitor if said specified voltage is applied to said memorycapacitor and said first load capacitor connected to each other inseries when said memory capacitor is in said second polarizationcondition.
 2. The ferroelectric memory device of claim 1 wherein saidmemory capacitor, said reference capacitor, said first load capacitorand said second load capacitors are all ferroelectric capacitors set ona same substrate and were produced at a same time in a same productionprocess.
 3. The ferroelectric memory device of claim 1 furthercomprising:a voltage applying means for applying said specified voltageas a readout voltage to said memory capacitor and said first loadcapacitor connected electrically to each other in series, said specifiedvoltage having a polarity which is different from the polarity of avoltage which results in said first polarization condition and applyinga same voltage as said readout voltage as a threshold-voltage-generatingvoltage to said reference capacitor and said second load capacitorconnected electrically to each other in series; and a memory contentjudging means for judging the memory content of said memory capacitor onthe basis of a first partial voltage generated at said memory capacitorwhen said readout voltage is applied and a second partial voltagegenerated at said reference capacitor when saidthreshold-voltage-generating voltage is applied.
 4. The ferroelectricmemory device of claim 2 further comprising:a voltage applying means forapplying said specified voltage as a readout voltage to said memorycapacitor and said first load capacitor connected electrically to eachother in series, said specified voltage having a polarity which isdifferent from the polarity of a voltage which results in said firstpolarization condition and applying a same voltage as said readoutvoltage as a threshold-voltage-generating voltage to said referencecapacitor and said second load capacitor connected electrically to eachother in series; and a memory content judging means for judging thememory content of said memory capacitor on the basis of a first partialvoltage generated at said memory capacitor when said readout voltage isapplied and a second partial voltage generated at said referencecapacitor when said threshold-voltage-generating voltage is applied. 5.The ferroelectric memory device of claim 3 wherein said referencecapacitor and said second load capacitor are electrically connected inseries to each other only when said voltage applying means is applyingsaid threshold-voltage-generating voltage.
 6. The ferroelectric memorydevice of claim 4 wherein said reference capacitor and said second loadcapacitor are electrically connected in series to each other only whensaid voltage applying means is applying saidthreshold-voltage-generating voltage.